The present invention relates to non-volatile semiconductor memory, more particularly to arrangement structures of a memory matrix for which a contrived method for reading data from the non-volatile semiconductor storage apparatuses is provided.
In a semiconductor storage apparatus, memory cells that can be set to three or more storage states are called multi-valued cells. For example, in a memory cell transistor, a multi-valued cell capable of storing 2-bit information by making it possible to set four values of current requires only half the cell area compared with a standard memory cell capable of storing 1-bit information. Such a multi-valued cell has an advantage in cost. However, since a multi-valued cell has several storage states, the gap between characteristic values in each state is smaller compared with the standard memory cell. Therefore, variations in the finished dimensions of the manufactured memory cells cause a high defective rate for the memory cells.
For this reason, in determining the arrangement structure of a multi-valued cell, it is important to apply a voltage to each terminal of a selected memory cell independently of the position of the selected memory cell within the arrangement. It is also desirable that the amount of parasitic current, which a sense amplifier detects, be made as small as possible. Here, the parasitic current is a current that depends on the data stored in adjacent cells other than the selected cell.
The arrangement structure of a multi-valued cell that avoids a parasitic current is disclosed in the Japanese Patent Application Laid-Open No. H6-318683. According to this arrangement structure, memory cells arranged in the column direction are divided into groups of eight memory cells which are electrically separated from each other. These eight memory cells which are electrically separated from each other are connected to main bit lines and main ground lines only when these eight memory cells are selected. When these eight memory cells are not selected, these electrically separated eight memory cells are electrically separated from the main bit lines and main ground lines, and are put in a floating state.
However, when a memory cell column is electrically separated for every eight cells, the area of the memory cell arrangement is increased. For example, when an electric separation means is constructed having an area equal to the area of one memory cell, the area of the resultant memory arrangement is increased by 12.5%. In addition, since unselected main bit lines and unselected main ground lines are put in a floating state, the access time is delayed, which is a problem.